The present invention relates to a high voltage, low on-resistance diffusion-self-alignment metal oxide semiconductor device.
In a field of metal oxide semiconductor devices, such as field effect transistors, conventionally called MOS FET, high voltage characteristics and semiconductor construction suited for integrated circuit technique are eagerly required. To achieve high voltage and rapid response, characteristics, diffusion-self-alignment MOS FET's (DSA-MOS-FET) have been developed. The DSA-MOS-FET can be provided with a short channel since the channel region is formed through the use of double diffusion techniques, whereupon it shows large transconductance and rapid saturation of the transconductance.
A typical construction of the DSA-MOST is shown in Thomas P. Cauge et al., U.S. Pat. No. 3,845,495 HIGH VOLTAGE, HIGH FREQUENCY DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE, patented on Oct. 29, 1974. This device consists of a silicon body of N.sup.- type, which acts as the drain region, a P.sup.+ channel region and an N.sup.+ source region formed on the central surface of the silicon body through the use of a double diffusion technique, and an N.sup.+ drain contact region formed circularly around the P.sup.+ channel region. Metallization formed above the P.sup.+ channel region via a thin oxide layer extends on a thick oxide layer formed on the silicon body to thereby outwardly spread the depletion region.
The above-mentioned DSA-MOST is not suited for integrated circuit technique since the isolation between two adjacent transistors is difficult to form. This is due to the fact that, in the above-mentioned DSA-MOST, the N-channel MOST is formed on the N-type semiconductor body with a construction in which the drain region is formed to surround the P.sup.+ channel region.